Modern integrated circuits (ICs), can include millions of transistors fabricated in and on a semiconductor substrate. In making a lithographic mask to fabricate such a complex device a circuit layout will pass through a variety of filters, checks, and modifications before being taped out to a mask. Ideally the process results in a mask that can be manufactured (lithographically printed) without defects and in an integrated circuit that is electrically functional.
The layout may contain standard cells and standard device designs as well as new cell and device designs, and must comply with rigid design rules that include minimum feature size, minimum spacing between device elements, and the like. An evolving layout likely passes through multiple simulations, many of which are time consuming. Short cuts are available to reduce simulation time, and hence cost, without sacrificing accuracy of the design. One method for providing approximate but fast evaluation of sensitivity of the layout to lithographic effects that can affect variability and yield is pattern matching. Pattern matching is used to determine lithographic or printability problems. Printability problems are problems in which a pattern on a mask, for example a particular array of lines and spaces, cannot be accurately reproduced on a semiconductor wafer by a lithographic process. In pattern matching single layer patterns that are known to cause printability problems are identified from different product layouts. These patterns form a library and designers and design tools avoid these patterns in implementing future designs. In practice an evolving layout design can be subjected to pattern matching software to identify patterns in the layout design that are similar to the library patterns. Patterns that are similar to library patterns are changed or replaced.
Although pattern matching can be successfully implemented to avoid most printability problems, pattern matching does not target multi-layer layout patterns that can cause electrical problems in the completed IC. Accordingly, it is desirable to provide methods for fabricating an integrated circuit that targets electrically correct layouts. In addition, it is desirable to provide methods for fabricating an integrated circuit that minimize design time and avoid electrical fault areas. Further, it is desirable to provide methods for fabricating an integrated circuit that reduce electrical variability and improve electrical performance. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.